The present invention relates to information processing and, more particularly, to optimization of memory addressing in systems.
Signal processors typically support addressing modes tailored for common signal processing algorithms. For example, digital signal processors commonly include features to optimize the performance of the Fast Fourier Transform (FFT). The Fast Fourier Transform typically uses multiple addressing modes including carry-reverse or bit reverse addressing. Other signal processing algorithms make extensive use of modulo addressing for easy array-based data and coefficient access. These addressing modes are often different than those modes supported in a more general-purpose processor. Often, the addressing modes for a general-purpose processor are based on efficient support for high-level languages like C, C++ and FORTRAN and not necessarily optimized for the operand reference patterns found in signal processing algorithms. In many cases, the entire organization of the processor""s pipeline is structured around the requirements of these basic addressing modes. As a result, many general-purpose processors do not support these advanced addressing modes. Typically, processor architectures are designed specifically to implement DSP-specific functions or general-purpose functions, but not both. Although general-purpose processors implement more than one general type of addressing mode, the addressing modes of such processors are not optimized for use with specialized applications such as digital signal processing, including certain audio processing functions.
As processing functions merge, more specialized functions need to be implemented by general-purpose processors, but most general-purpose processors are not capable of supporting advanced memory addressing modes. Implementing advanced memory addressing modes inside a general-purpose processor typically requires a restructuring of the pipeline architecture before such advanced addressing modes may be implemented.